Intel Corporation
Intel Corporation
Intel Corporation व्यक्तिगत कंप्यूटरों, डेटा केंद्रों, क्लाउड अवसंरचना, एज सिस्टम, नेटवर्किंग और 5G वातावरणों में उपयोग की जाने वाली कंप्यूटिंग प्रौद्योगिकियों का विकास और निर्माण करती है। इसके उत्पाद पोर्टफोलियो में Intel Core, Xeon और Atom प्रोसेसर के साथ-साथ अलग ग्राफिक्स, AI एक्सेलेरेटर, सिलिकॉन फोटोनिक्स, एम्बेडेड समाधान तथा नेटवर्किंग और स्टोरेज प्रौद्योगिकियाँ शामिल हैं। कंपनी प्रदर्शन और सुरक्षा पर ध्यान केंद्रित करते हुए सॉफ्टवेयर टूल और तकनीकी संसाधनों के माध्यम से डेवलपर्स का भी सहयोग करती है तथा AI-सक्षम कंप्यूटिंग को आगे बढ़ाने में योगदान देती है।

Pre-Silicon Verification Engineer, PLL/FLL Clock IP

Verify Intel PLL and FLL clock-generator IP before silicon, developing UVM test environments and investigating design issues. Lead mixed-signal validation and work with design teams to refine IP features.

विवरण

  • Build SystemVerilog and UVM test benches, verification environments, and tests.
  • Verify PLL and FLL clock-generator IP against microarchitecture specifications.
  • Maintain and improve verification infrastructure and methods across IP generations.
  • Investigate and identify root causes of pre-silicon issues in the verification environment.
  • Write test plans and take part in technical reviews with design teams.
  • Work with architects, RTL developers, and analog design teams.
  • Lead mixed-signal validation, including AMS simulations and schematic debugging.
  • Resolve issues that involve multiple teams.
  • Help define and refine architectural and microarchitectural features for IP design.

आवश्यकताएँ

  • Bachelor’s degree in Electrical or Computer Engineering or a related field with at least 4 years of relevant experience; or a master’s degree with at least 3 years; or a PhD with at least 1 year.
  • At least 2 years of experience with design verification and validation methods, including UVM, SystemVerilog, and standard EDA tools.
  • At least 2 years of experience using scripting languages such as Python and Perl.
  • Advanced skill in writing and debugging SystemVerilog UVM code.
  • Familiarity with PLL/FLL or SoC clocking and related RTL development.
  • Ability to work across teams with architects, RTL developers, and analog design teams.
  • Careful documentation of test plans and debugging of pre-silicon issues.
  • Proactive problem-solving and root-cause analysis skills.

लाभ

  • Competitive pay.
  • Stock bonuses.
  • Health benefits.
  • Retirement benefits.
  • Vacation benefits.
  • Hybrid work arrangement with time split between on-site and off-site work.

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