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Intel Corporation
Intel Corporation
Sponzor vizuma H1BLogistikaProizvodnjaSvetovanje
Intel Corporation razvija in izdeluje računalniške tehnologije, ki se uporabljajo v osebnih računalnikih, podatkovnih centrih, infrastrukturi v oblaku, robnih sistemih, omrežjih in okoljih 5G. Njen portfelj vključuje procesorje Intel Core, Xeon in Atom ter diskretne grafične rešitve, pospeševalnike umetne inteligence, silicijevo fotoniko, vgrajene rešitve in tehnologije za omrežno povezovanje ter shranjevanje podatkov. Podjetje razvijalce podpira z orodji za razvoj programske opreme in tehničnimi viri, pri čemer se osredotoča na zmogljivost, varnost in napredek računalništva, ki ga omogoča umetna inteligenca.
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Delovna mesta v podjetju

Pre-Silicon Verification Engineer, PLL/FLL Clock IP

Verify Intel PLL and FLL clock-generator IP before silicon, developing UVM test environments and investigating design issues. Lead mixed-signal validation and work with design teams to refine IP features.

USZdružene države AmerikeAZArizonaCAKalifornijaMAMassachusettsOROregonTXTeksas
122.440 $ – 172.860 $ / leto
HibridnoPolni delovni časSrednja ravenSeniorZahtevani Jezik: angleščinaInženir
PerlPython

Opis

  • Build SystemVerilog and UVM test benches, verification environments, and tests.
  • Verify PLL and FLL clock-generator IP against microarchitecture specifications.
  • Maintain and improve verification infrastructure and methods across IP generations.
  • Investigate and identify root causes of pre-silicon issues in the verification environment.
  • Write test plans and take part in technical reviews with design teams.
  • Work with architects, RTL developers, and analog design teams.
  • Lead mixed-signal validation, including AMS simulations and schematic debugging.
  • Resolve issues that involve multiple teams.
  • Help define and refine architectural and microarchitectural features for IP design.

Zahteve

  • Bachelor’s degree in Electrical or Computer Engineering or a related field with at least 4 years of relevant experience; or a master’s degree with at least 3 years; or a PhD with at least 1 year.
  • At least 2 years of experience with design verification and validation methods, including UVM, SystemVerilog, and standard EDA tools.
  • At least 2 years of experience using scripting languages such as Python and Perl.
  • Advanced skill in writing and debugging SystemVerilog UVM code.
  • Familiarity with PLL/FLL or SoC clocking and related RTL development.
  • Ability to work across teams with architects, RTL developers, and analog design teams.
  • Careful documentation of test plans and debugging of pre-silicon issues.
  • Proactive problem-solving and root-cause analysis skills.

Ugodnosti

  • Competitive pay.
  • Stock bonuses.
  • Health benefits.
  • Retirement benefits.
  • Vacation benefits.
  • Hybrid work arrangement with time split between on-site and off-site work.

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