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Normal Computing
Normal Computing
51 – 200 Angajați
Informațiile disponibile despre companie menționează că Normal Computing a fost fondată în 2022, dar nu descriu produsele, serviciile, domeniul de activitate sau contextul angajărilor sale. Sunt necesare mai multe detalii specifice companiei pentru a oferi o prezentare utilă celor care caută un loc de muncă.
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FPGA Hardware Engineer

Bring physics-inspired ASIC designs to life for AI and semiconductor infrastructure, owning RTL implementation, PCIe validation, FPGA prototyping, and silicon bring-up.

USStatele Unite ale AmericiiCACaliforniaNYNew York
250.000 $ – 340.000 $ / an
HibridNormă întreagăNivel mediuSeniorLimbă Obligatorie: englezăInginer hardware
C++DockerPython

Descriere

  • Lead the selection, procurement, and bring-up of FPGA prototyping platforms for pre-silicon RTL validation and software development.
  • Adapt complex ASIC RTL for FPGA targets, including multi-clock architectures, CDC bridges, and timing closure on dense designs.
  • Integrate internal designs with third-party and vendor IP.
  • Guide use of the AMD/Xilinx ecosystem, including Vivado IP Integrator, transceivers, and memory controllers.
  • Design, implement, and validate high-speed I/O, particularly PCIe for accelerator cards in standard servers.
  • Build FPGA-based test designs for silicon bring-up, device characterization, and automated test environments.
  • Develop Python and C++ hardware abstraction software, register-map generation, and automated build and regression workflows.
  • Diagnose timing and functional issues in the lab using ILA/Vivado Analyzer, oscilloscopes, logic analyzers, and BER and eye-diagram characterization.
  • Collaborate daily with silicon, EDA, and research teams throughout the FPGA lifecycle.

Cerințe

  • Demonstrated industry experience taking FPGA designs from RTL through timing closure to validated hardware.
  • Expert knowledge of SystemVerilog and/or VHDL for synthesis.
  • Strong proficiency with Xilinx Vivado, including synthesis, place and route, timing closure, and the IP catalog.
  • Practical experience implementing and debugging PCIe, AXI/AHB, SPI, UART, JTAG, and other common interfaces.
  • Strong Python skills for automation, testing, and build tools.
  • Strong board-level bring-up and hands-on lab debugging skills.
  • Ability to work independently, adapt quickly, and solve ambiguous problems across hardware, software, and physics.
  • Experience with verification frameworks such as Cocotb or UVM is a bonus.
  • Experience deploying machine learning models to FPGAs or building real-time, sub-microsecond signal-processing pipelines is a bonus.
  • Mixed-signal ASIC experience is a bonus.
  • SERDES tuning and signal-integrity fundamentals are a bonus.
  • Experience with hardware CI/CD using GitLab CI and Docker-based build and test workflows is a bonus.

Beneficii

  • Equity.
  • An equal opportunity employer committed to diversity and inclusion.
  • Reasonable accommodations for people with disabilities.

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