
Hardware Engineer, Performance Modeling
Normal ComputingBuild transaction-level performance models for Normal Computing’s physics-inspired AI ASICs. Compare model predictions with RTL, FPGA, and synthesis results to inform hardware architecture.


Build transaction-level performance models for Normal Computing’s physics-inspired AI ASICs. Compare model predictions with RTL, FPGA, and synthesis results to inform hardware architecture.

Lead design-for-test for Normal Computing’s physics-inspired ASICs, covering scan, ATPG, MBIST, and silicon testability. Drive DFT architecture, verification, manufacturing readiness, and tapeout.

Design mixed-signal circuits, memory, and analog IP for Normal Computing’s applied AI and semiconductor systems. Build silicon technology spanning early circuit design through silicon bring-up.

Develop next-generation high-speed networking hardware at Cisco through ASIC package and interconnect design, simulation, and validation. Focus on signal and power integrity across advanced packaging.

Bring physics-inspired ASIC designs to life for AI and semiconductor infrastructure, owning RTL implementation, PCIe validation, FPGA prototyping, and silicon bring-up.