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Normal Computing
Normal Computing
51 – 200 Angajați
Informațiile disponibile despre companie menționează că Normal Computing a fost fondată în 2022, dar nu descriu produsele, serviciile, domeniul de activitate sau contextul angajărilor sale. Sunt necesare mai multe detalii specifice companiei pentru a oferi o prezentare utilă celor care caută un loc de muncă.
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Senior DFT Hardware Engineer

Lead design-for-test for Normal Computing’s physics-inspired ASICs, covering scan, ATPG, MBIST, and silicon testability. Drive DFT architecture, verification, manufacturing readiness, and tapeout.

USStatele Unite ale AmericiiCACaliforniaHibridNormă întreagăSeniorLiderLimbă Obligatorie: englezăInginer hardware
Python

Descriere

  • Lead DFT architecture and implementation for next-generation physics-inspired ASICs, from early RTL through tapeout and silicon bring-up.
  • Set scan, ATPG, MBIST, and boundary-scan strategies.
  • Develop chip-level DFT architecture spanning scan insertion and compression, ATPG, MBIST, boundary scan/JTAG, and test access infrastructure.
  • Coordinate DFT insertion and integration across RTL, synthesis, and physical design.
  • Lead DFT verification, pattern generation, fault coverage analysis, test-mode validation, and signoff through tapeout.
  • Provide manufacturing partners with production-ready test patterns and collateral, including ATE integration, bring-up, and diagnosis documentation.
  • Build scalable DFT flows, automation, and practices with industry-standard EDA tools.
  • Set technical requirements, oversee contracted DFT work, and assess external partner deliverables.
  • Work across RTL, verification, physical design, silicon product engineering, manufacturing, and external partner teams.

Cerințe

  • At least seven years implementing DFT for complex ASICs or SoCs, including successful tapeouts.
  • Hands-on strength in scan insertion, ATPG, scan compression, fault coverage analysis, and test pattern generation.
  • Demonstrated experience with MBIST, boundary scan/JTAG, and DFT integration across RTL and gate-level designs.
  • Proficiency with Siemens Tessent, Synopsys TestMAX, or Cadence Modus.
  • Sound knowledge of RTL design, synthesis, static timing analysis, and physical design considerations.
  • Experience delivering manufacturing test patterns and working with silicon product engineering or ATE teams.
  • Strong scripting ability in Python, Tcl, or similar languages.
  • Able to independently own DFT architecture, lead cross-functional technical decisions, and communicate across design, verification, and product engineering teams.
  • Experience creating DFT architecture and methodology from the ground up for a new ASIC program.
  • Familiarity with IEEE 1500, IEEE 1687 (IJTAG), hierarchical DFT, and advanced scan compression techniques.
  • Experience with memory redundancy, built-in self-repair (BISR), silicon diagnosis, and yield improvement.
  • Experience working with external DFT implementation partners or managing outsourced deliverables.
  • Exposure to AI accelerators, memory-intensive architectures, or unconventional computing systems.
  • Experience using AI-assisted or agentic tools to automate silicon design and verification workflows.

Beneficii

  • Equal opportunity employer.
  • Inclusive workplace committed to diversity.
  • Reasonable accommodations available for people with disabilities.

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