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FPGA Engineer, Chip Design (Remote, India)
Build chip-design evaluations and reference RTL for AI systems, reviewing verification, timing, synthesis, and PPA across semiconductor workflows. This remote role is based in India.
भारत₹12,00,000 – ₹20,00,000 / वर्ष
रिमोटपूर्णकालिकमध्य स्तरवरिष्ठआवश्यक भाषा: अंग्रेज़ीहार्डवेयर इंजीनियरविवरण
- Create practical assessments spanning RTL design, verification, synthesis, physical design, and sign-off.
- Develop reference designs in Verilog, SystemVerilog, or VHDL, with testbenches, constraints, and expected outputs.
- Set grading standards and validation approaches that match professional engineering practice.
- Inspect AI-produced RTL, testbenches, hardware designs, and implementation outputs for functional faults and design shortcomings.
- Investigate verification failures, coverage gaps, timing violations, and inefficient power, performance, and area choices.
- Assess designs for correctness, timing compliance, resource use, and implementation quality.
- Set up and maintain EDA environments where AI agents can run realistic chip-design flows.
- Use relevant tools such as Synopsys, Cadence, Siemens, AMD/Xilinx Vivado, and Intel Quartus.
- Create assessments for synthesis quality, place-and-route outcomes, static timing analysis, and timing closure.
- Turn recurring AI-agent errors into new evaluation cases and progressively harder engineering tasks.
- Partner with engineering and research teams to strengthen evaluation environments, test methods, and technical benchmarks.
- Automate design flows, tests, and results analysis with scripting languages.
- Record reference solutions, design assumptions, failure cases, and evaluation methods.
आवश्यकताएँ
- Bring 3–5 years of practical ASIC or FPGA design experience, ideally spanning multiple stages of the digital design flow.
- Hold a B.E., B.Tech, or M.Tech in Electrical Engineering, Electronics Engineering, VLSI, or a related field.
- Have strong RTL skills in Verilog, SystemVerilog, or VHDL.
- Have hands-on design verification experience, including testbench development, debugging, coverage analysis, and UVM or similar methods.
- Be familiar with EDA tools and workflows from Synopsys, Cadence, Siemens, AMD/Xilinx, or Intel.
- Understand logic synthesis, place-and-route, static timing analysis, timing constraints, and timing closure.
- Apply sound engineering judgement to power, performance, and area (PPA) trade-offs.
- Have carried at least one project from specification through implementation or tape-out.
- Bring strong debugging, analytical, and problem-solving skills, and explain clearly why a design passes or fails.
- Python, Tcl, or Perl experience for design-flow automation is an advantage.
- Familiarity with open-source tools such as Yosys, OpenROAD, Verilator, or cocotb is beneficial.
- Interest in AI engineering evaluations, reinforcement-learning environments, or model post-training is welcome but not required.
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