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Cadence Design Systems
Cadence Design Systems
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Cadence Design Systems develops computational software, hardware, and intellectual property for electronics and system design. With more than 30 years of software expertise and a focus on intelligent system design, the company helps leading organizations turn design concepts into advanced electronic products. Its technologies support work across hyperscale computing, 5G communications, automotive, mobile, aerospace, consumer, industrial, and healthcare applications.
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Chip Lead, Physical Design Director

Lead Cadence’s physical design and design-for-test efforts for advanced SoC projects, guiding RTL-to-GDS delivery for data center, automotive, and AI customers. Own PPA, timing, power, and schedule closure across complex semiconductor engagements.

USUnited StatesCACaliforniaTXTexasOn-siteFull-timeSeniorEnglish RequiredArt Director
Node.jsPerlPython

Description

  • Lead Physical Design and Design for Test teams on complex customer SoC projects from RTL or netlist through GDS.
  • Partner directly with customers throughout each engagement, from kickoff through final GDS delivery.
  • Make technical decisions, resolve design trade-offs, and develop solutions that meet customer PPA and schedule targets.
  • Advise customers on suitable foundry processes, technology nodes, libraries, and memory compilers.
  • Define sign-off criteria that balance product features and implementation cost.
  • Work with internal Cadence teams on technical presentations and the advancement of internal AI initiatives.
  • Coordinate with customer or internal RTL and synthesis teams to meet key metrics before the physical design phase gate.
  • Collaborate with Cadence tools R&D to improve implementation tools and methodologies.
  • Capture and share best practices and lessons learned to increase efficiency, project success, and AI adoption.

Requirements

  • At least 15 years of industry experience in physical design.
  • Bachelor’s degree in computer science, computer engineering, electrical engineering, or a related discipline.
  • Strong understanding of digital design and semiconductor fundamentals, plus static timing analysis and timing constraints.
  • Hands-on experience with IC digital implementation flows and backend EDA tools, including place and route, clock tree synthesis, IR drop analysis, backend timing, and power closure.
  • Proven ability to complete design closure for top-level chip projects.
  • Expertise in PPA optimization and balancing performance, power, and area against demanding design targets.
  • Experience working with advanced process nodes at 7nm or below.
  • Proficiency with scripting languages such as Tcl, Perl, or Python.
  • Strong customer-facing communication and problem-solving abilities.
  • Commitment to continuous learning and broadening technical expertise.
  • Experience building effective technical partnerships with RTL, DFT, CAD, and library teams.
  • Preferred: Master’s degree in computer science, computer engineering, electrical engineering, or a related discipline.
  • Preferred: Experience with front-end EDA and IC digital implementation flows, including synthesis, DFT, and logical equivalence checking.
  • Preferred: Experience with Cadence tools such as Genus, Innovus, Conformal, Tempus, Modus, or comparable tools including ICC, ICC2, DC, or PrimeTime.
  • Preferred: Experience with advanced process nodes at 5nm or below.
  • Preferred: Expertise in domains such as CPUs, GPUs, AI engines, networks on chip, or high-speed interfaces.
  • Preferred: Experience with 3D IC design.

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