Firmware Engineer
Normal Computing51 – 200 कर्मचारी
Develop embedded SoC firmware and APIs for Normal Computing’s AI and silicon systems. Build environments for development, simulation, debugging, verification, and stress testing.
खोलें
Hardware Engineer, Performance Modeling
Build transaction-level performance models for Normal Computing’s physics-inspired AI ASICs. Compare model predictions with RTL, FPGA, and synthesis results to inform hardware architecture.
विवरण
- Develop and maintain approximate, cycle-accurate transaction-level models of compute tiles, memory hierarchies, and interconnects using SystemC, C++, or Python.
- Use transaction-level model (TLM) and RTL results alongside physical design data to calibrate latency, bandwidth, energy, utilization, and occupancy parameters for end-to-end AI workload predictions.
- Provide the TLM as a reference model for design verification, with transaction-level scoreboards and performance checks.
- Work with design verification (DV) and RTL teams to confirm RTL behavior and keep the TLM aligned with it.
- Schedule modeling work in line with the hardware roadmap.
- Study the performance impact of buffer sizes, interface widths, scheduling policies, and bus configurations.
- Use modeling findings to recommend changes to architecture and hardware teams.
- Compare TLM results with RTL, FPGA prototypes, and synthesis results.
- Partner with architecture, hardware design, and DV teams to refine the end-to-end system.
आवश्यकताएँ
- At least five years of performance modeling experience at a major semiconductor company.
- Demonstrated ability to understand architectures and translate them into efficient modeling code.
- Experience with a range of modeling techniques and programming languages.
- Strong written and verbal communication skills.
- Experience with AI acceleration hardware is a plus.
- Experience with architecture-level modeling and cost tools such as AccelForge, Timeloop/Accelergy, CACTI, McPAT, or gem6 is a plus.
- Experience with design verification methodology is a plus.
- Hands-on experience using LLMs or agentic tools in development workflows is a plus.
- Exposure to analog, mixed-signal, or unconventional computing is a plus.
- Experience with memory interfaces such as LPDDR, HBM, and DDR, and other I/O is a plus.
लाभ
- Equal opportunity employer committed to diversity and inclusion.
- Reasonable accommodations are available for individuals with disabilities.
संबंधित नौकरियाँ
Senior DFT Hardware Engineer
Normal Computing51 – 200 कर्मचारी
Lead design-for-test for Normal Computing’s physics-inspired ASICs, covering scan, ATPG, MBIST, and silicon testability. Drive DFT architecture, verification, manufacturing readiness, and tapeout.
खोलें
Senior Analog Hardware Engineer
Normal Computing51 – 200 कर्मचारी
Design mixed-signal circuits, memory, and analog IP for Normal Computing’s applied AI and semiconductor systems. Build silicon technology spanning early circuit design through silicon bring-up.
खोलें
ASIC Packaging Signal and Power Integrity Engineer
Cisco
संयुक्त राज्य
कैलिफ़ोर्निया$1,55,000 – $2,22,600 / वर्ष
हाइब्रिडपूर्णकालिकमध्य स्तरवरिष्ठआवश्यक भाषा: अंग्रेज़ीहार्डवेयर इंजीनियरDevelop next-generation high-speed networking hardware at Cisco through ASIC package and interconnect design, simulation, and validation. Focus on signal and power integrity across advanced packaging.
खोलें
FPGA Hardware Engineer
Normal Computing51 – 200 कर्मचारी
संयुक्त राज्यकैलिफ़ोर्निया
न्यूयॉर्क$2,50,000 – $3,40,000 / वर्ष
हाइब्रिडपूर्णकालिकमध्य स्तरवरिष्ठआवश्यक भाषा: अंग्रेज़ीहार्डवेयर इंजीनियरBring physics-inspired ASIC designs to life for AI and semiconductor infrastructure, owning RTL implementation, PCIe validation, FPGA prototyping, and silicon bring-up.
खोलें