Build transaction-level performance models for Normal Computing’s physics-inspired AI ASICs. Compare model predictions with RTL, FPGA, and synthesis results to inform hardware architecture.
At Normal Computing, turn Thermo In-Memory Computing concepts into silicon for AI inference. Design memory architectures, interfaces, models, and test-chip tapeouts.
संयुक्त राज्य
कैलिफ़ोर्नियाहाइब्रिडपूर्णकालिकमध्य स्तरवरिष्ठआवश्यक भाषा: अंग्रेज़ीफ्रंटएंड इंजीनियरसॉफ्टवेयर इंजीनियरExtend compiler support for emerging LLM architectures, from attention variants and MoE routing to quantization and numeric formats. Validate model bring-up on simulators and FPGA prototypes for Normal Computing’s in-memory AI hardware.
Develop embedded SoC firmware and APIs for Normal Computing’s AI and silicon systems. Build environments for development, simulation, debugging, verification, and stress testing.
Lead design-for-test for Normal Computing’s physics-inspired ASICs, covering scan, ATPG, MBIST, and silicon testability. Drive DFT architecture, verification, manufacturing readiness, and tapeout.
संयुक्त राज्यकैलिफ़ोर्नियाहाइब्रिडपूर्णकालिकलीडआवश्यक भाषा: अंग्रेज़ीफुल-स्टैक इंजीनियरसॉफ्टवेयर इंजीनियरLead packaging, testing, validation, yield, and manufacturing for Normal Computing’s custom AI inference silicon. Build the team and processes needed to bring memory products into high-volume production.
Shape Normal Computing’s AI inference hardware, from accelerator to rack, for its applied AI and silicon infrastructure products. Lead thermal design, mechanical integration, manufacturability, qualification, and supplier builds.
Develop LLM inference algorithms for Normal Computing’s in-memory AI hardware. Collaborate with hardware and architecture teams to co-design numerical methods, benchmarks, and prototypes.
Lead silicon development planning, delivery milestones, risk management, and executive updates at Normal Computing. The company develops AI hardware and software for semiconductor infrastructure.
Design mixed-signal circuits, memory, and analog IP for Normal Computing’s applied AI and semiconductor systems. Build silicon technology spanning early circuit design through silicon bring-up.
संयुक्त राज्यकैलिफ़ोर्नियाDevelop code generation, scheduling, and memory planning for Normal Computing’s custom AI hardware. Optimize LLM inference across simulators, FPGA prototypes, and future silicon.
संयुक्त राज्यकैलिफ़ोर्निया
न्यूयॉर्कDesign runtime software for Normal Computing’s memory-centric AI hardware, leading architecture, hardware abstraction, and LLM inference performance.
संयुक्त राज्यकैलिफ़ोर्नियाLead full-cycle hiring for specialized silicon and ASIC engineering roles at Normal Computing. Recruit across applied AI, semiconductor hardware, and AI infrastructure.
संयुक्त राज्यकैलिफ़ोर्नियाCoordinate interviews, manage Ashby and support global hiring operations at Normal Computing, an applied AI and semiconductor infrastructure company.
संयुक्त राज्यकैलिफ़ोर्नियान्यूयॉर्कBring physics-inspired ASIC designs to life for AI and semiconductor infrastructure, owning RTL implementation, PCIe validation, FPGA prototyping, and silicon bring-up.
