
Hardware Engineer, Performance Modeling
Normal ComputingBuild transaction-level performance models for Normal Computing’s physics-inspired AI ASICs. Compare model predictions with RTL, FPGA, and synthesis results to inform hardware architecture.


Build transaction-level performance models for Normal Computing’s physics-inspired AI ASICs. Compare model predictions with RTL, FPGA, and synthesis results to inform hardware architecture.

Develop embedded SoC firmware and APIs for Normal Computing’s AI and silicon systems. Build environments for development, simulation, debugging, verification, and stress testing.

Lead design-for-test for Normal Computing’s physics-inspired ASICs, covering scan, ATPG, MBIST, and silicon testability. Drive DFT architecture, verification, manufacturing readiness, and tapeout.

Design mixed-signal circuits, memory, and analog IP for Normal Computing’s applied AI and semiconductor systems. Build silicon technology spanning early circuit design through silicon bring-up.

Bring physics-inspired ASIC designs to life for AI and semiconductor infrastructure, owning RTL implementation, PCIe validation, FPGA prototyping, and silicon bring-up.