Cisco
Cisco
Cisco एक एंटरप्राइज़ प्रौद्योगिकी कंपनी है, जिसका मुख्य ध्यान नेटवर्किंग, सुरक्षा और डिजिटल अवसंरचना पर है। इसके उत्पादों और सेवाओं में राउटर, स्विच, ऑप्टिकल ट्रांसीवर, प्रोग्रामेबल सिलिकॉन, एज कंप्यूटिंग प्लेटफ़ॉर्म, Webex सहयोग उपकरण, ऑब्ज़र्वेबिलिटी उत्पाद, कृत्रिम बुद्धिमत्ता-सक्षम सॉफ़्टवेयर और क्लाउड-प्रबंधित सेवाएँ शामिल हैं। Cisco उद्यमों, सेवा प्रदाताओं और सरकारों को सेवा देता है तथा प्रौद्योगिकी, पेशेवर सेवाओं, प्रशिक्षण और निरंतर सहायता के माध्यम से बड़े पैमाने के नेटवर्क और डेटा केंद्रों के डिज़ाइन, संचालन और सुरक्षा में सहयोग करता है।

ASIC Packaging Signal and Power Integrity Engineer

Develop next-generation high-speed networking hardware at Cisco through ASIC package and interconnect design, simulation, and validation. Focus on signal and power integrity across advanced packaging.

विवरण

  • Create and document design rules for ultra-high-speed signaling.
  • Meet product goals for power, performance, and area.
  • Analyze signal and power integrity in package substrates.
  • Work with layout teams to optimize interposer, substrate, and PCB designs.
  • Develop and document ASIC packages for high-volume, high-quality production.
  • Run post-layout extraction and prepare reports.
  • Coordinate with system partners, vendors, and design leads.
  • Address complex technical issues using advanced technology design rules.
  • Define, design, and verify next-generation ASIC packaging for Cisco platforms.

आवश्यकताएँ

  • Bachelor’s degree in Electrical Engineering and 4+ years of relevant signal and power integrity experience; or a master’s degree and 2+ years; or a PhD and 0+ years; equivalent related work experience is also accepted.
  • Knowledge of high-speed design principles, including transmission line theory, electromagnetics, scattering parameters, and impedance network analysis.
  • Experience applying high-speed design principles to 56G PAM4 SerDes architectures, channel modeling, and BER prediction.
  • Experience with pre- and post-layout signal and power integrity simulations using Cadence Sigrity, Ansys HFSS, and Keysight ADS.
  • Experience reviewing layouts and validating physical designs with Cadence APD and Ansys EM flows.
  • Experience using SPICE for circuit-level analysis, signal modeling, and performance validation.
  • Ability to explain technical concepts to varied audiences in writing and verbally.
  • Experience with signal and power integrity for HBM or high-speed memory interfaces is preferred.
  • Experience with UCIe or proprietary die-to-die interfaces is preferred.
  • Experience with advanced packaging, including CoWoS, EMIB, and interposer-based designs, is preferred.
  • Vector network analysis experience is preferred.
  • IBIS experience is preferred.

लाभ

  • Medical, dental, and vision insurance.
  • 401(k) plan with Cisco matching contributions.
  • Paid parental leave.
  • Short- and long-term disability coverage.
  • Basic life insurance.
  • Cisco restricted stock unit grants may be offered and vest with continued employment.
  • 10 paid holidays per full calendar year.
  • One floating holiday for non-exempt employees.
  • One paid day off for the employee’s birthday.
  • Paid year-end holiday shutdown.
  • Four paid days off for personal wellness.
  • 16 days of paid vacation per full calendar year for non-exempt employees.
  • Eligible exempt employees receive flexible vacation time with no defined limit.
  • 80 hours of sick time on the hire date and each January 1 thereafter.
  • Carry forward up to 80 unused sick hours each year.
  • Additional paid time away for critical or emergency family needs.
  • Optional 10 paid volunteer days per full calendar year.
  • Annual bonuses may be available for non-sales roles.

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