Cisco

Sponzor vizuma H1B Podjetje Strojna oprema Varnost

Cisco je tehnološko podjetje za poslovne uporabnike, osredotočeno na omrežja, varnost in digitalno infrastrukturo. Njegov portfelj vključuje usmerjevalnike, stikala, optične oddajnike in sprejemnike, programirljive silicijeve komponente, platforme za robno računalništvo, orodja za sodelovanje Webex, izdelke za opazljivost, programsko opremo z zmogljivostmi umetne inteligence ter storitve, upravljane v oblaku. Cisco oskrbuje podjetja, ponudnike storitev in državne ustanove ter s tehnologijo, strokovnimi storitvami, usposabljanjem in stalno podporo podpira načrtovanje, delovanje in varovanje obsežnih omrežij in podatkovnih centrov.

Delovna mesta v podjetju

ASIC Packaging Signal and Power Integrity Engineer

Develop next-generation high-speed networking hardware at Cisco through ASIC package and interconnect design, simulation, and validation. Focus on signal and power integrity across advanced packaging.

pred 2 tednoma

Združene države Amerike

Kalifornija

155.000 $ – 222.600 $ / leto

Hibridno Polni delovni čas Srednja raven Senior Zahtevani Jezik: angleščina Inženir strojne opreme

Opis

Create and document design rules for ultra-high-speed signaling.
Meet product goals for power, performance, and area.
Analyze signal and power integrity in package substrates.
Work with layout teams to optimize interposer, substrate, and PCB designs.
Develop and document ASIC packages for high-volume, high-quality production.
Run post-layout extraction and prepare reports.
Coordinate with system partners, vendors, and design leads.
Address complex technical issues using advanced technology design rules.
Define, design, and verify next-generation ASIC packaging for Cisco platforms.

Zahteve

Bachelor’s degree in Electrical Engineering and 4+ years of relevant signal and power integrity experience; or a master’s degree and 2+ years; or a PhD and 0+ years; equivalent related work experience is also accepted.
Knowledge of high-speed design principles, including transmission line theory, electromagnetics, scattering parameters, and impedance network analysis.
Experience applying high-speed design principles to 56G PAM4 SerDes architectures, channel modeling, and BER prediction.
Experience with pre- and post-layout signal and power integrity simulations using Cadence Sigrity, Ansys HFSS, and Keysight ADS.
Experience reviewing layouts and validating physical designs with Cadence APD and Ansys EM flows.
Experience using SPICE for circuit-level analysis, signal modeling, and performance validation.
Ability to explain technical concepts to varied audiences in writing and verbally.
Experience with signal and power integrity for HBM or high-speed memory interfaces is preferred.
Experience with UCIe or proprietary die-to-die interfaces is preferred.
Experience with advanced packaging, including CoWoS, EMIB, and interposer-based designs, is preferred.
Vector network analysis experience is preferred.
IBIS experience is preferred.

Ugodnosti

Medical, dental, and vision insurance.
401(k) plan with Cisco matching contributions.
Paid parental leave.
Short- and long-term disability coverage.
Basic life insurance.
Cisco restricted stock unit grants may be offered and vest with continued employment.
10 paid holidays per full calendar year.
One floating holiday for non-exempt employees.
One paid day off for the employee’s birthday.
Paid year-end holiday shutdown.
Four paid days off for personal wellness.
16 days of paid vacation per full calendar year for non-exempt employees.
Eligible exempt employees receive flexible vacation time with no defined limit.
80 hours of sick time on the hire date and each January 1 thereafter.
Carry forward up to 80 unused sick hours each year.
Additional paid time away for critical or emergency family needs.
Optional 10 paid volunteer days per full calendar year.
Annual bonuses may be available for non-sales roles.

Sorodna delovna mesta

51 – 200 Zaposleni

Združene države Amerike

Kalifornija Hibridno Polni delovni čas Srednja raven Senior Zahtevani Jezik: angleščina Inženir strojne opreme

C++Python

Build transaction-level performance models for Normal Computing’s physics-inspired AI ASICs. Compare model predictions with RTL, FPGA, and synthesis results to inform hardware architecture.

Odpri

51 – 200 Zaposleni

Združene države Amerike

Kalifornija Hibridno Polni delovni čas Srednja raven Senior Zahtevani Jezik: angleščina Inženir strojne opreme

Develop embedded SoC firmware and APIs for Normal Computing’s AI and silicon systems. Build environments for development, simulation, debugging, verification, and stress testing.

Odpri

51 – 200 Zaposleni

Združene države Amerike

Kalifornija Hibridno Polni delovni čas Senior Vodja Zahtevani Jezik: angleščina Inženir strojne opreme

Python

Lead design-for-test for Normal Computing’s physics-inspired ASICs, covering scan, ATPG, MBIST, and silicon testability. Drive DFT architecture, verification, manufacturing readiness, and tapeout.

Odpri

51 – 200 Zaposleni

Združene države Amerike

Kalifornija Hibridno Polni delovni čas Srednja raven Senior Zahtevani Jezik: angleščina Inženir strojne opreme

Design mixed-signal circuits, memory, and analog IP for Normal Computing’s applied AI and semiconductor systems. Build silicon technology spanning early circuit design through silicon bring-up.

Odpri

51 – 200 Zaposleni

Združene države Amerike

Kalifornija

New York

250.000 $ – 340.000 $ / leto

Hibridno Polni delovni čas Srednja raven Senior Zahtevani Jezik: angleščina Inženir strojne opreme

C++Docker Python

Bring physics-inspired ASIC designs to life for AI and semiconductor infrastructure, owning RTL implementation, PCIe validation, FPGA prototyping, and silicon bring-up.

Odpri

ASIC Packaging Signal and Power Integrity Engineer

Develop next-generation high-speed networking hardware at Cisco through ASIC package and interconnect design, simulation, and validation. Focus on signal and power integrity across advanced packaging.

Opis

Zahteve

Ugodnosti

Sorodna delovna mesta

Hardware Engineer, Performance Modeling

Firmware Engineer

Senior DFT Hardware Engineer

Senior Analog Hardware Engineer

FPGA Hardware Engineer