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Cisco is an enterprise technology company focused on networking, security, and digital infrastructure. Its portfolio includes routers, switches, optical transceivers, programmable silicon, edge computing platforms, Webex collaboration tools, observability products, AI-enabled software, and cloud-managed services. Cisco serves enterprises, service providers, and governments, supporting the design, operation, and security of large-scale networks and data centers through technology, professional services, training, and ongoing support.
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ASIC Packaging Signal and Power Integrity Engineer

Develop next-generation high-speed networking hardware at Cisco through ASIC package and interconnect design, simulation, and validation. Focus on signal and power integrity across advanced packaging.

USUnited StatesCACalifornia
$155,000 – $222,600 / year
HybridFull-timeMiddleSeniorEnglish RequiredHardware Engineer

Description

  • Create and document design rules for ultra-high-speed signaling.
  • Meet product goals for power, performance, and area.
  • Analyze signal and power integrity in package substrates.
  • Work with layout teams to optimize interposer, substrate, and PCB designs.
  • Develop and document ASIC packages for high-volume, high-quality production.
  • Run post-layout extraction and prepare reports.
  • Coordinate with system partners, vendors, and design leads.
  • Address complex technical issues using advanced technology design rules.
  • Define, design, and verify next-generation ASIC packaging for Cisco platforms.

Requirements

  • Bachelor’s degree in Electrical Engineering and 4+ years of relevant signal and power integrity experience; or a master’s degree and 2+ years; or a PhD and 0+ years; equivalent related work experience is also accepted.
  • Knowledge of high-speed design principles, including transmission line theory, electromagnetics, scattering parameters, and impedance network analysis.
  • Experience applying high-speed design principles to 56G PAM4 SerDes architectures, channel modeling, and BER prediction.
  • Experience with pre- and post-layout signal and power integrity simulations using Cadence Sigrity, Ansys HFSS, and Keysight ADS.
  • Experience reviewing layouts and validating physical designs with Cadence APD and Ansys EM flows.
  • Experience using SPICE for circuit-level analysis, signal modeling, and performance validation.
  • Ability to explain technical concepts to varied audiences in writing and verbally.
  • Experience with signal and power integrity for HBM or high-speed memory interfaces is preferred.
  • Experience with UCIe or proprietary die-to-die interfaces is preferred.
  • Experience with advanced packaging, including CoWoS, EMIB, and interposer-based designs, is preferred.
  • Vector network analysis experience is preferred.
  • IBIS experience is preferred.

Benefits

  • Medical, dental, and vision insurance.
  • 401(k) plan with Cisco matching contributions.
  • Paid parental leave.
  • Short- and long-term disability coverage.
  • Basic life insurance.
  • Cisco restricted stock unit grants may be offered and vest with continued employment.
  • 10 paid holidays per full calendar year.
  • One floating holiday for non-exempt employees.
  • One paid day off for the employee’s birthday.
  • Paid year-end holiday shutdown.
  • Four paid days off for personal wellness.
  • 16 days of paid vacation per full calendar year for non-exempt employees.
  • Eligible exempt employees receive flexible vacation time with no defined limit.
  • 80 hours of sick time on the hire date and each January 1 thereafter.
  • Carry forward up to 80 unused sick hours each year.
  • Additional paid time away for critical or emergency family needs.
  • Optional 10 paid volunteer days per full calendar year.
  • Annual bonuses may be available for non-sales roles.

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