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AccelerComm Ltd
AccelerComm Ltd
51 – 200 Angajați
ConsultanțăIndustria prelucrătoareTelecomunicații
AccelerComm Ltd dezvoltă tehnologii de comunicații de înaltă performanță pentru rețelele 5G. Algoritmii săi de comunicații brevetați și proprietatea intelectuală pentru nivelul fizic sunt concepute pentru rețelele de acces radio, ajutând operatorii, producătorii de echipamente și furnizorii de cipuri să abordeze provocările legate de capacitatea rețelei, latență, consumul de energie și eficiența spectrală. Compania activează în domeniile telecomunicațiilor, producției și consultanței și contribuie la colaborarea din industrie prin participarea la O-RAN ALLIANCE.
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Locurile de muncă ale companiei

Senior Design Team Leader – ASIC/FPGA 5G Satellite Systems

Lead ASIC and FPGA Layer 1 IP development for power-efficient 5G satellite and non-terrestrial communications at AccelerComm. Guide engineering teams, customer delivery, and cross-functional technical planning.

GBRegatul UnitHibridNormă întreagăSeniorLimbă Obligatorie: englezăDesigner
C++

Descriere

  • Contribute to 5G satellite base stations and non-terrestrial communications technology
  • Define the technical roadmap for improving power efficiency in the next generation of space-qualified devices
  • Deliver developed technology to customers
  • Support technical decisions and company-wide planning with Algorithm, System Architecture, and Software teams
  • Provide technical direction to ensure projects are delivered successfully and on schedule
  • Lead the team while building shared expertise and supporting individual growth
  • Convert product requirements into hardware deliverables alongside senior hardware engineers
  • Participate in customer discussions during presales and product development
  • Oversee FPGA and ASIC implementation using industry-standard methods, including UVM-based testbench development
  • Advance engineering methods, processes, and design practices, incorporating AI where useful
  • Mentor, coach, and provide team members with regular feedback

Cerințe

  • Demonstrated success building and leading high-performing, collaborative teams
  • Expertise in RTL design with Verilog and SystemVerilog for complex ASIC and FPGA products
  • Strong experience delivering digital designs for ASIC and FPGA platforms
  • Experience optimizing timing and hardware resources for high-throughput data or signal-processing applications
  • Experience with power-management techniques, synthesis, and timing analysis
  • Advanced proficiency with EDA tools for simulation and synthesis
  • Knowledge of project-management methods used throughout the design lifecycle, including agile and waterfall approaches
  • Knowledge of requirements capture and traceability practices
  • Knowledge of communications signal-processing algorithms, including error correction, equalization, channel estimation, and beamforming
  • Understanding of UVM verification techniques or practical experience applying UVM to IP verification
  • Experience with high-speed on-chip and off-chip interfaces such as AMBA, PCIe, or JESD
  • Understanding of C++ and SystemC for design modeling and integration
  • Experience with Technology Readiness Models
  • Understanding of system architecture within a multidisciplinary project team

Beneficii

  • Salary package determined by skills and experience
  • Annual performance bonus of up to 20% of salary
  • Periodic grants of EMI share options
  • Pension
  • Private health insurance
  • Flexible working hours
  • Hybrid working

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