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AccelerComm Ltd
AccelerComm Ltd
51 – 200 Xodimlar
Ishlab chiqarishKonsaltingTelekommunikatsiyalar
AccelerComm Ltd 5G tarmoqlari uchun yuqori samarali aloqa texnologiyalarini ishlab chiqadi. Kompaniyaning patentlangan aloqa algoritmlari va fizik qatlamga oid IP yechimlari radio ulanish tarmoqlari uchun mo‘ljallangan bo‘lib, operatorlar, uskunalar ishlab chiqaruvchilar va kremniy chiplarini yetkazib beruvchilarga tarmoq sig‘imi, kechikish, quvvat sarfi hamda spektral samaradorlik bilan bog‘liq muammolarni hal qilishda yordam beradi. Kompaniya telekommunikatsiya, ishlab chiqarish va konsalting sohalarida faoliyat yuritadi hamda O-RAN ALLIANCEdagi ishtiroki orqali sohadagi hamkorlikka hissa qo‘shadi.
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Kompaniyadagi ish o‘rinlari

Senior Design Team Leader – ASIC/FPGA 5G Satellite Systems

Lead ASIC and FPGA Layer 1 IP development for power-efficient 5G satellite and non-terrestrial communications at AccelerComm. Guide engineering teams, customer delivery, and cross-functional technical planning.

GBBuyuk BritaniyaGibridTo‘liq stavkaSeniorTalab Qilinadigan Til: inglizchaDizayner
C++

Tavsif

  • Contribute to 5G satellite base stations and non-terrestrial communications technology
  • Define the technical roadmap for improving power efficiency in the next generation of space-qualified devices
  • Deliver developed technology to customers
  • Support technical decisions and company-wide planning with Algorithm, System Architecture, and Software teams
  • Provide technical direction to ensure projects are delivered successfully and on schedule
  • Lead the team while building shared expertise and supporting individual growth
  • Convert product requirements into hardware deliverables alongside senior hardware engineers
  • Participate in customer discussions during presales and product development
  • Oversee FPGA and ASIC implementation using industry-standard methods, including UVM-based testbench development
  • Advance engineering methods, processes, and design practices, incorporating AI where useful
  • Mentor, coach, and provide team members with regular feedback

Talablar

  • Demonstrated success building and leading high-performing, collaborative teams
  • Expertise in RTL design with Verilog and SystemVerilog for complex ASIC and FPGA products
  • Strong experience delivering digital designs for ASIC and FPGA platforms
  • Experience optimizing timing and hardware resources for high-throughput data or signal-processing applications
  • Experience with power-management techniques, synthesis, and timing analysis
  • Advanced proficiency with EDA tools for simulation and synthesis
  • Knowledge of project-management methods used throughout the design lifecycle, including agile and waterfall approaches
  • Knowledge of requirements capture and traceability practices
  • Knowledge of communications signal-processing algorithms, including error correction, equalization, channel estimation, and beamforming
  • Understanding of UVM verification techniques or practical experience applying UVM to IP verification
  • Experience with high-speed on-chip and off-chip interfaces such as AMBA, PCIe, or JESD
  • Understanding of C++ and SystemC for design modeling and integration
  • Experience with Technology Readiness Models
  • Understanding of system architecture within a multidisciplinary project team

Imtiyozlar

  • Salary package determined by skills and experience
  • Annual performance bonus of up to 20% of salary
  • Periodic grants of EMI share options
  • Pension
  • Private health insurance
  • Flexible working hours
  • Hybrid working

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