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Normal Computing
Normal Computing
51 – 200 Darbinieki
The available profile information identifies Normal Computing as a company founded in 2022, but does not describe its products, services, industry, or hiring context. More company-specific details are needed to provide a useful overview for job seekers.
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Vakances uzņēmumā

Memory Architect

At Normal Computing, turn Thermo In-Memory Computing concepts into silicon for AI inference. Design memory architectures, interfaces, models, and test-chip tapeouts.

USAmerikas Savienotās ValstisCAKalifornijaHibrīdiPilna slodzeVidējais līmenisVecākais speciālistsNepieciešamā Valoda: angļuArhitekts
C++Python

Apraksts

  • Turn Thermo In-Memory Computing concepts from theory into silicon.
  • Redesign memory access paths, array organization, and microarchitecture to coordinate memory operations with high-performance computing.
  • Target 100–1000× improvements in AI inference performance.
  • Report to the Director of Silicon Engineering.
  • Collaborate with scientists, microarchitects, and physical and analog design engineers.
  • Develop a standard-cell library that combines digital compute primitives with ThermoDRAM compute primitives.
  • Translate compute primitives into a high-performance Compute In-Memory System.
  • Manage technical relationships with major manufacturers, from PDK acquisition through test-chip tapeout and production silicon.
  • Define processing-in-memory architecture, memory requirements, floorplans, read/write circuitry, and row and column decoders.
  • Architect local and global datapaths, segmented buses, and on-die fabrics.
  • Manage power distribution and budgets, thermal limits, redundancy, ECC, retention, and yield considerations.
  • Manage PDK and fab access, design-rule assessment, shuttle tapeout planning, test-chip content, schedules, and bring-up.
  • Work with analog engineers on primitive device libraries and set architectural performance requirements.
  • Define custom memory interfaces, including SERDES, PCIe, Ethernet, DDR5, LP6, or HBM-class interfaces.
  • Oversee SPICE, analytical, and cycle-level models for performance, power, and yield.
  • Work with performance and machine learning engineers to validate workload-level gains.

Prasības

  • Extensive experience in memory architecture or circuit design at a memory manufacturer or memory-focused computing company.
  • In-depth knowledge of 1T, 3T, 6T, and 8T SRAM cells; DRAM bitcells; capacitance; sensing; read and write operations; core timing; retention; and reliability.
  • Practical experience with embedded memory or random-access memory technology and PDKs.
  • Experience developing memory test chips through tapeout.
  • Ability to connect SPICE-level circuit behavior with architecture-level performance and power models.
  • Strong programming fundamentals in Python, C, C++, or another language for modeling and performance prediction.
  • Experience with RTL and SystemVerilog.
  • Experience with memory interface types.
  • Excellent written and verbal communication skills.

Priekšrocības

  • The company is an equal opportunity employer committed to diversity and inclusion.
  • Reasonable accommodations are available for individuals with disabilities.
  • Applicant privacy protections apply to employment-related personal information.

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