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Senior ASIC Digital Design Leader, CPU Subsystems and Complex SoCs
Lead ASIC and SoC digital design from architecture and RTL through tapeout and post-silicon validation. Guide silicon photonics and Client Optics Group engineering teams building Cisco optical networking products.
विवरण
- Lead digital design from pre-silicon RTL through GDS2 signoff, FPGA prototyping, lab validation, and ATE bring-up.
- Architect and design complex digital blocks and CPU subsystems.
- Coordinate with digital, analog and mixed-signal, verification, DFT, physical design, firmware, FPGA, CAD, packaging, and post-silicon validation teams.
- Set digital architecture, interface requirements, implementation plans, and design methodology.
- Lead block development and support full-chip integration of high-speed IP, including ODSP, D2D, SerDes XSR, SerDes PAM4 integrated drivers and TIA, and control functions.
- Partner with verification teams to reach functional closure and review coverage and its metrics.
- Prepare designs for physical implementation and support post-silicon bring-up through production release.
- Contribute to firmware architecture and firmware-based verification.
- Write top-level and block specifications for high-speed datapaths and low-speed control planes, covering timing, power budgets, and hardware-firmware partitioning.
- Simulate, verify, and debug issues independently; support SerDes and DSP IP integration and verification.
- Support synthesis, timing closure, DFT, low-power design, automation scripts, and QOR metric processing.
आवश्यकताएँ
- Bachelor’s or master’s degree in electrical engineering, electronics engineering, or a related discipline; a master’s degree is strongly preferred.
- 12–16 years of industry experience in hands-on digital design, including FSM and CPU subsystems, complex SoCs, and FPGA validation.
- At least 6 years of technical leadership experience.
- Familiarity with SPI, I2C, APB, AXI, or comparable interfaces, as well as high-speed SerDes, Ethernet, D2D PHY IP, and protocols.
- Strong command of ASIC and SoC design flows, including SystemVerilog RTL development, simulation, lint, CDC/RDC, synthesis, formal and equivalence checking, DFT, and implementation handoff.
- Solid understanding of front-end design and development, with exposure to backend tools for CDC, synthesis, LEC, and DFT.
- Strong collaboration, communication, and organizational abilities.
- Strong analytical, problem-solving, and debugging abilities.
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