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Signal and Power Integrity Technical Leader | Cisco, San Jose Hybrid

Lead signal and power integrity engineering for Cisco’s advanced ASIC packaging and networking silicon. Guide SI/PI design, verification, packaging architecture, and technical teams for high-performance systems.

USStatele Unite ale AmericiiCACalifornia
214.100 $ – 309.800 $ / an
HibridNormă întreagăSeniorLimbă Obligatorie: englezăInginer full-stackInginer software
Python

Descriere

  • Develop packaging solutions for next-generation ASICs
  • Manage Cisco’s Silicon Packaging Signal and Power Integrity team
  • Define, design, and validate ASIC packaging for Cisco platforms
  • Create and implement design rules for ultra-high-speed signaling
  • Balance power, performance, and area targets
  • Evaluate signal and power integrity at the substrate level
  • Partner with layout teams on interposer, substrate, and PCB solutions
  • Develop and document ASIC packages for high-volume, high-quality production
  • Complete post-layout extraction and performance reporting
  • Work with system partners, suppliers, and design leaders to resolve complex technical problems
  • Establish processes, methodologies, and tools for advanced ASIC and package development
  • Contribute to chip architecture and high-performance ASIC definition, architecture, and design
  • Assess complex IC and analog/mixed-signal circuit designs
  • Coach signal integrity team members and early-career engineers
  • Guide packaging and hardware teams toward technical requirements and innovative outcomes
  • Advance design reviews, postmortems, and continuous improvement across multidisciplinary engineering teams

Cerințe

  • Bachelor’s degree in Electrical Engineering with 10+ years of relevant signal or power integrity experience; master’s degree with 8+ years; or PhD with 5+ years
  • Experience supporting multiple high-speed ASIC tape-outs from a packaging perspective
  • Experience with 56G PAM4 or faster signaling
  • Experience with high-speed SerDes architectures
  • Background in channel modeling
  • Experience predicting bit error rates
  • Understanding of transmission-line theory and electromagnetics
  • Strong knowledge of scattering and impedance network parameters
  • Practical laboratory experience using Keysight ADS, Ansys HFSS or EM flow, and Cadence APD for layout review
  • Experience with SPICE
  • Technical leadership experience with small to medium-sized teams is preferred
  • Experience with advanced process nodes, including 5nm, 3nm, or smaller, is preferred
  • Experience with HBM or high-speed memory-interface signal integrity is preferred
  • Experience with die-to-die interfaces such as UCIe or proprietary technologies is preferred
  • Experience with advanced packaging, including CoWoS, EMIB, and interposer-based designs, is preferred
  • Experience with MATLAB or Python scripting is preferred
  • Experience with Raptor-X is preferred
  • Experience with vector network analysis is preferred
  • Experience with IBIS is preferred

Beneficii

  • Medical, dental, and vision coverage
  • 401(k) plan with Cisco matching contributions
  • Paid parental leave
  • Short- and long-term disability insurance
  • Basic life insurance
  • Cisco restricted stock unit grants, subject to eligibility
  • Ten paid holidays per full calendar year
  • One floating holiday for non-exempt employees
  • One paid birthday day off
  • Paid year-end holiday shutdown
  • Four paid personal wellness days
  • Sixteen paid vacation days per full calendar year for non-exempt employees
  • Flexible vacation time for exempt employees
  • Eighty hours of sick leave provided upon hire and each January 1
  • Carryover of up to 80 unused sick hours
  • Additional paid leave for critical or emergency family situations
  • Optional ten paid volunteer days per full calendar year
  • Annual bonuses for non-sales roles, subject to Cisco policies
  • Access to a worldwide network of doers and experts
  • Opportunities for professional growth and development
  • Collaborative and empathetic team environment

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