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GlobalFoundries
GlobalFoundries
H1B Visa SponsorHardwareManufacturing
GlobalFoundries is a semiconductor manufacturer serving high-growth markets through process technology, chip design support, development, and fabrication services. Its work combines engineering and manufacturing across a large, diverse workforce and production footprint spanning the United States, Europe, and Asia. For job seekers, GlobalFoundries offers opportunities connected to semiconductor technology, hardware manufacturing, process development, and advanced fabrication.
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Quantum PDK Design Enablement Engineer

Develop DRC, LVS, and PEX solutions for GlobalFoundries semiconductor foundry operations. Advance PDK automation and AI/ML-assisted verification workflows.

USUnited StatesNYNew York
$88,000 – $154,000 / year
On-siteFull-timeMiddleSeniorEnglish RequiredDesigner
PerlPythonShell Scripting

Description

  • Create, code, qualify, and maintain DRC, LVS, and PEX rule decks and related PDK components
  • Convert process integration requirements, design rules, device definitions, and electrical models into production-ready physical verification and extraction solutions
  • Build regression and testing methods that assess rule-deck accuracy, coverage, performance, scalability, and compatibility
  • Investigate complex DRC, LVS, and PEX problems, determine root causes, and resolve discrepancies with cross-functional teams
  • Partner with process technology, design rule, compact modeling, reliability, circuit design, layout, and EDA teams
  • Create automation and AI/ML-assisted methods for rule generation, test generation, coverage analysis, error classification, anomaly detection, debugging, and ongoing PDK verification
  • Improve physical verification and extraction flows for accuracy, execution time, memory efficiency, scalability, usability, and production deployment
  • Lead PDK quality and release preparation through qualification, regression testing, documentation, change management, and customer-informed enhancements
  • Conduct work safely and contribute to Environmental, Health, Safety & Security programs
  • Undertake additional projects and assignments as required

Requirements

  • Bachelor’s degree in Electrical Engineering, Computer Engineering, Microelectronics, Computer Science, Applied Physics, or a related technical discipline
  • Relevant experience in semiconductor PDK development, physical verification, EDA, IC physical design, parasitic extraction, or a related area, with required years determined by the applicable GF career level
  • Experience developing, coding, debugging, or qualifying DRC and/or LVS rules
  • Knowledge of parasitic resistance and capacitance extraction, interconnect modeling, layout-dependent effects, and their influence on circuit performance
  • Working knowledge of CMOS process technologies, semiconductor devices, layout rules, interconnect structures, and design-to-manufacturing relationships
  • Experience with standard physical verification and/or extraction environments and rule-deck development practices
  • Experience using Python, Tcl, Perl, shell scripting, or comparable programming and scripting languages
  • Ability to diagnose complex technical issues, apply structured root-cause analysis, and turn findings into durable engineering solutions
  • Fluent written and spoken English
  • Master’s degree or PhD in a related discipline preferred
  • Experience creating and releasing production PDK DRC, LVS, and/or PEX rule decks preferred
  • Experience with Siemens Calibre, Synopsys IC Validator, Cadence Pegasus/PVS, or comparable tools preferred
  • Experience developing PEX technology files, RC extraction flows, process-corner models, and silicon-to-model correlation preferred
  • Experience building automated regression environments, rule-coverage metrics, test structures, or PDK qualification methods preferred
  • Experience applying AI/ML, generative AI, or data-driven methods to semiconductor design enablement preferred
  • Understanding of the relationships among process integration, design rules, OPC/lithography, device modeling, reliability, extraction, and circuit design preferred
  • Experience working directly with EDA suppliers and internal or external design teams preferred
  • Strong written and verbal communication skills preferred
  • Strong planning and organizational abilities preferred

Benefits

  • Travel of up to 10% may be required
  • The employer provides equal employment opportunities
  • Reasonable accommodation is available during the employment process

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