NVIDIA
NVIDIA
NVIDIA गेमिंग, डेटा सेंटर, क्लाउड कंप्यूटिंग, स्वास्थ्य सेवा, विनिर्माण, ऑटोमोटिव और रोबोटिक्स सहित विभिन्न क्षेत्रों में उपयोग की जाने वाली त्वरित कंप्यूटिंग और कृत्रिम बुद्धिमत्ता प्रौद्योगिकियाँ विकसित करती है। इसका कार्य ग्राफ़िक्स प्रोसेसिंग यूनिट, AI प्लेटफ़ॉर्म, सिमुलेशन और उद्योग-केंद्रित समाधानों तक फैला हुआ है। इनमें सहयोगात्मक 3D वर्कफ़्लो के लिए NVIDIA Omniverse, स्वायत्त वाहन विकास के लिए NVIDIA DRIVE और स्वास्थ्य सेवा अनुप्रयोगों के लिए NVIDIA Clara शामिल हैं। कंपनी उन्नत कंप्यूटिंग, सिमुलेशन और AI-आधारित विश्लेषणों को समर्थन देने वाले बुनियादी ढाँचे और सॉफ़्टवेयर पर काम करने वाली बड़ी तकनीकी टीमों को एक साथ लाती है।

Senior Circuit Timing Engineer, NVIDIA (Remote, California)

Design NVIDIA processor circuits for hardware security, adaptive clocking, and power management. Lead timing signoff and transistor-level analysis, and apply AI/ML methods to silicon design.

विवरण

  • Contribute to processor design using deep-submicron technologies
  • Design circuits for hardware security, adaptive clocking, and power management
  • Lead timing analysis and signoff for digital, semi-custom, and analog mixed-signal circuit macros
  • Validate timing with Nanotime, PrimeTime, Tempus, and SPICE simulation tools
  • Partner across teams to improve power, performance, area, and reliability in next-generation products
  • Create timing models and methodologies for custom macro designs
  • Design and time transistor-level circuits, enter schematics, and deliver layouts
  • Apply AI/ML techniques to design processes and methodologies
  • Coordinate with PD, DFX, Clocks, and other teams on timing signoff strategy, constraints, power and timing convergence, DFT, and timing ECOs

आवश्यकताएँ

  • BSEE or MS in electrical or computer engineering preferred, or equivalent experience
  • At least 6 years of digital circuit design experience with a master's degree, or 8 years with a bachelor's degree
  • Strong understanding of deep-submicron process issues and digital circuit design techniques
  • Expertise with industry-standard STA tools, including Nanotime, PrimeTime, Tempus, and other timing analysis tools
  • Practical experience running SPICE simulations, EM/IR analysis, and static timing analysis and closure
  • Demonstrated experience generating and managing timing constraints
  • Expertise in analyzing and fixing timing paths through ECOs, including crosstalk and glitch noise
  • Solid understanding of extracted timing models and using .libs in PrimeTime
  • Knowledge of process-variation modeling and design convergence in multi-GHz deep-submicron technology
  • Demonstrated ownership and hands-on work across the silicon design flow, from microarchitecture and RTL through backend execution, including custom and semi-custom circuit design, synthesis, automatic place and route, STA, and PVerf
  • Demonstrated ability to characterize and debug post-silicon designs
  • Record of independently driving complex features from initial concept through tape-out and validation
  • Knowledge of timing-closure strategies for digital logic and macros within AMS designs or IPs

लाभ

  • Equity compensation
  • Benefits

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