NVIDIA
NVIDIA
NVIDIA develops accelerated computing and artificial intelligence technologies used across gaming, data centers, cloud computing, healthcare, manufacturing, automotive, and robotics. Its work spans graphics processing units, AI platforms, simulation, and industry-focused solutions, including NVIDIA Omniverse for collaborative 3D workflows, NVIDIA DRIVE for autonomous vehicle development, and NVIDIA Clara for healthcare applications. The company brings together large technical teams working on the infrastructure and software that support advanced computing, simulation, and AI-driven analytics.

Senior Circuit Timing Engineer, NVIDIA (Remote, California)

Design NVIDIA processor circuits for hardware security, adaptive clocking, and power management. Lead timing signoff and transistor-level analysis, and apply AI/ML methods to silicon design.

Description

  • Contribute to processor design using deep-submicron technologies
  • Design circuits for hardware security, adaptive clocking, and power management
  • Lead timing analysis and signoff for digital, semi-custom, and analog mixed-signal circuit macros
  • Validate timing with Nanotime, PrimeTime, Tempus, and SPICE simulation tools
  • Partner across teams to improve power, performance, area, and reliability in next-generation products
  • Create timing models and methodologies for custom macro designs
  • Design and time transistor-level circuits, enter schematics, and deliver layouts
  • Apply AI/ML techniques to design processes and methodologies
  • Coordinate with PD, DFX, Clocks, and other teams on timing signoff strategy, constraints, power and timing convergence, DFT, and timing ECOs

Requirements

  • BSEE or MS in electrical or computer engineering preferred, or equivalent experience
  • At least 6 years of digital circuit design experience with a master's degree, or 8 years with a bachelor's degree
  • Strong understanding of deep-submicron process issues and digital circuit design techniques
  • Expertise with industry-standard STA tools, including Nanotime, PrimeTime, Tempus, and other timing analysis tools
  • Practical experience running SPICE simulations, EM/IR analysis, and static timing analysis and closure
  • Demonstrated experience generating and managing timing constraints
  • Expertise in analyzing and fixing timing paths through ECOs, including crosstalk and glitch noise
  • Solid understanding of extracted timing models and using .libs in PrimeTime
  • Knowledge of process-variation modeling and design convergence in multi-GHz deep-submicron technology
  • Demonstrated ownership and hands-on work across the silicon design flow, from microarchitecture and RTL through backend execution, including custom and semi-custom circuit design, synthesis, automatic place and route, STA, and PVerf
  • Demonstrated ability to characterize and debug post-silicon designs
  • Record of independently driving complex features from initial concept through tape-out and validation
  • Knowledge of timing-closure strategies for digital logic and macros within AMS designs or IPs

Benefits

  • Equity compensation
  • Benefits

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