Ceva, Inc.
Ceva, Inc.
Ceva, Inc. develops semiconductor and software intellectual property for smart edge devices that need reliable connectivity, sensing, and on-device inference. Its portfolio includes DSP cores, deep-learning technology, communication processors, and wireless solutions used across consumer IoT, mobile, automotive, and other connected applications. With more than three decades of experience, the company supports chip and product developers through licensed IP deployed in billions of chips worldwide.

Wireless Platform Architect (Hybrid, Israel)

Lead end-to-end architecture for Wi-Fi, Bluetooth, and UWB radio subsystems at Ceva. Guide SoC integration, validation, power and performance optimization, and customer productization.

Description

  • Own RSS end-to-end architecture and hardware/software partitioning across radio, PHY, MAC, CPU/MCU, memory, power, clock, reset, and related subsystem interfaces.
  • Define the hardware interfaces, state machines, control flows, and operating sequences required for multi-protocol operation and interoperability.
  • Establish sleep and wake modes, testability provisions, security mechanisms, and debug capabilities.
  • Lead RSS power, performance, and area optimization, including competitive benchmarking with emphasis on low-power system efficiency.
  • Partner with RF, PHY and algorithm, hardware, firmware, verification, and integration teams from early system studies through RTL/FPGA validation and system bring-up.
  • Work with customers to integrate RSS into their SoCs and resolve system architecture, interoperability, validation, and productization challenges.

Requirements

  • Bachelor’s or master’s degree in electrical engineering.
  • Demonstrated experience defining systems and architectures for hardware-based wireless communications.
  • Experience with wireless standards such as Wi-Fi, Bluetooth, cellular, or UWB.
  • Strong knowledge of low-power design and system architecture.
  • Understanding of SoC architecture and IP integration, including interfaces, memory, interrupts, clocks, resets, and power domains.
  • Deep knowledge of VLSI and ASIC development processes and methodologies.
  • Understanding of ASIC productization and system bring-up processes.
  • Strong technical leadership and the ability to drive architectural decisions.
  • Collaborative team contributor with effective communication skills.
  • Strong customer-facing technical capability, including translating customer requirements and SoC constraints into system architecture.
  • Flexible, innovative approach to technical problem-solving.
  • Knowledge of RF integration, control, and calibration.
  • Knowledge of signal processing and PHY architecture.
  • Knowledge of MAC-layer architecture.
  • Experience with embedded processors or MCUs and low-level firmware architecture.
  • Experience with laboratory work, silicon validation, and bring-up.

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