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AccelerComm Ltd develops high-performance communications technology for 5G networks. Its patented communications algorithms and physical-layer IP are designed for radio access networks, helping operators, equipment manufacturers, and silicon vendors address network capacity, latency, power consumption, and spectral-efficiency challenges. The company operates across telecommunications, manufacturing, and consulting, and contributes to industry collaboration through participation in the O-RAN ALLIANCE.
Senior ASIC and FPGA Design Team Leader at AccelerComm
Lead the development of power-efficient, space-qualified 5G base-station hardware at AccelerComm. Guide ASIC and FPGA IP delivery, engineering teams, customer technology work, and design strategy.
Description
- Set the technical roadmap for improving power efficiency in the newest generation of space-qualified devices
- Deliver hardware technology to customers
- Define strategic direction for technical decisions and company-level planning
- Work closely with Algorithm, System Architecture, and Software teams
- Provide technical leadership to ensure projects are delivered successfully and on schedule
- Manage and develop the team by building knowledge and supporting professional growth
- Convert product requirements into hardware deliverables with the executive team
- Assist customers through presales and product-development discussions
- Oversee FPGA and ASIC implementation using established industry techniques
- Develop UVM-based verification testbenches
- Lead engineering methods, processes, and design practices, incorporating AI where practical
- Mentor team members, provide coaching, and deliver regular feedback
Requirements
- Demonstrated success leading teams and delivering complex intellectual property
- Expertise in RTL design with Verilog and SystemVerilog for complex ASIC and FPGA products
- Strong experience delivering digital designs for ASIC and FPGA platforms
- Experience optimizing timing and hardware resources for high-throughput data or signal-processing systems
- Experience with power-management methods, synthesis, and timing analysis
- Advanced proficiency with EDA tools for simulation and synthesis
- Understanding of project-management methods across the full design lifecycle, including agile and waterfall approaches
- Knowledge of requirements capture and traceability practices
- Knowledge of communications signal-processing algorithms, such as error correction, equalisation, channel estimation, and beamforming, is desirable
- Understanding of UVM verification methods or practical experience applying UVM to IP verification is desirable
- Experience with high-speed interfaces including AMBA, PCI-E, or JESD is desirable
- Understanding of C++ or SystemC for design modelling and integration is desirable
- Experience with Technology Readiness Models is desirable
- Understanding of system architecture within a multidisciplinary project team is desirable
Benefits
- Salary is competitive and determined by skills and experience
- Annual performance-based bonus of up to 20% of salary
- Periodic grants of EMI share options
- Pension scheme
- Private health insurance
- Flexible working hours
- Hybrid working arrangement
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