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Senior ASIC DFT Engineer - Austin, Hybrid

Develop DFT logic, test architectures, and validation flows for Cisco Silicon One networking chips. Partner with RTL, verification, physical design, and multifunctional teams.

USStatele Unite ale AmericiiCACaliforniaTXTexas
139.300 $ – 203.600 $ / an
HibridNormă întreagăSeniorLiderLimbă Obligatorie: englezăInginer

Descriere

  • Join the Silicon One development organization as an ASIC DFT Engineer
  • Partner with front-end RTL, design verification, backend physical design, and multifunctional teams
  • Interpret chip architecture and establish DFT requirements early in the design cycle
  • Implement hardware DFT capabilities for ATE, in-system testing, debugging, and diagnostics
  • Create DFT IP and integrate full-chip testability features through coordinated RTL development
  • Support test-logic integration and validation across implementation and post-silicon flows
  • Advance DFT and quality processes through implementation and post-silicon validation
  • Support physical design signoff activities
  • Develop reusable test and debug strategies for new silicon device models, bare die, and stacked die
  • Develop solutions and troubleshoot issues with limited mentorship

Cerințe

  • Bachelor’s or master’s degree in electrical or computer engineering
  • Seven or more years of experience
  • Experience with current DFT, test, and silicon engineering practices
  • Experience with JTAG protocols and Scan and BIST architectures, including memory BIST and boundary scan
  • Experience with ATPG and EDA tools including TestMax, Tetramax, Tessent, and PrimeTime
  • Experience with gate-level simulation and debugging using VCS or other simulators
  • Experience in post-silicon validation and debugging
  • Ability to work with ATE patterns and P1687
  • Ability to develop solutions and debug with limited mentorship
  • Verilog design experience, including custom DFT logic and IP integration
  • Familiarity with functional verification
  • DFT CAD development experience spanning test architecture, methodology, and infrastructure
  • Experience with test static timing analysis
  • Experience validating silicon after production using DFT patterns
  • SystemVerilog logic-equivalence checking and test-timing validation skills

Beneficii

  • Medical, dental, and vision insurance
  • 401(k) plan with Cisco matching contributions
  • Paid parental leave
  • Short- and long-term disability coverage
  • Basic life insurance
  • Cisco restricted stock unit grants may be available
  • Ten paid holidays per full calendar year
  • One floating holiday for non-exempt employees
  • Paid birthday day off
  • Paid year-end holiday shutdown
  • Four paid personal wellness days
  • Sixteen paid vacation days for non-exempt employees
  • Flexible vacation time off program for exempt employees
  • Eighty hours of sick time provided upon hire and each January 1 thereafter
  • Up to eighty hours of unused sick time carried forward
  • Additional paid time away for critical or emergency family issues
  • Optional ten paid volunteer days per full calendar year
  • Annual bonuses for non-sales roles, subject to Cisco policies

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