Cisco
Cisco
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Cisco Signal and Power Integrity Technical Leader

Lead signal and power integrity engineering for advanced Cisco Silicon One ASIC packaging. Direct SI/PI design, verification, packaging development, and multidisciplinary technical teams.

विवरण

  • Create and maintain design rules for ultra-high-speed signaling
  • Evaluate substrate signal integrity and power integrity performance
  • Partner with layout engineers on interposer, substrate, and PCB implementations
  • Develop and document ASIC packages for high-volume, high-quality production releases
  • Complete post-layout extraction and generate analysis reports
  • Work with system partners, vendors, and design leads to solve complex technical problems
  • Establish processes, methodologies, and tools for advanced ASIC and package development
  • Contribute to chip architecture decisions and high-performance ASIC design
  • Assess complex IC and analog/mixed-signal circuit designs
  • Manage the Silicon Packaging Signal and Power Integrity Team
  • Coach signal integrity specialists and junior engineers
  • Guide packaging and hardware teams toward required technical specifications
  • Advance design reviews, postmortems, and continuous improvement across multidisciplinary engineering groups

आवश्यकताएँ

  • Bachelor’s degree in Electrical Engineering with at least 10 years of relevant signal or power integrity experience, master’s degree with at least 8 years, or PhD with at least 5 years
  • Experience supporting multiple high-speed ASIC tape-outs from the package perspective
  • Professional experience with 56G PAM4 or faster signaling
  • Understanding of high-speed SerDes architectures, channel modeling, BER prediction, transmission line theory, and electromagnetics
  • Strong knowledge of scattering parameters and impedance network parameters
  • Practical laboratory experience using Keysight ADS, Ansys HFSS or EM flow, and Cadence APD for layout review
  • Experience working with SPICE
  • Preferred: experience leading small or medium-sized technical teams
  • Preferred: experience with advanced process nodes at 5nm, 3nm, or smaller
  • Preferred: experience with HBM or high-speed memory-interface signal integrity
  • Preferred: experience with UCIe or proprietary die-to-die interfaces
  • Preferred: experience with advanced packaging technologies including CoWoS, EMIB, and interposer-based designs
  • Preferred: experience using MATLAB or Python scripting, Raptor-X, vector network analysis, and IBIS

लाभ

  • Medical, dental, and vision insurance
  • 401(k) plan with Cisco matching contributions
  • Paid parental leave
  • Short- and long-term disability insurance
  • Basic life insurance
  • Cisco restricted stock unit grants may be available
  • 10 paid holidays per full calendar year
  • One floating holiday for non-exempt employees
  • One paid day off for the employee’s birthday
  • Paid year-end holiday shutdown
  • Four paid personal wellness days
  • 16 paid vacation days per full calendar year for non-exempt employees
  • Flexible vacation time-off program for exempt employees
  • 80 hours of sick leave provided on the hire date and each January 1 thereafter
  • Ability to carry forward up to 80 hours of unused sick leave
  • Additional paid time away for critical or emergency family matters
  • Optional 10 paid volunteer days per full calendar year
  • Annual bonuses for non-sales roles, subject to Cisco policies

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