Marvell Technology
Marvell Technology
5,001 – 10,000 Employees
ConsultingEnterpriseManufacturing
Marvell Technology develops semiconductor and infrastructure solutions for consumer and enterprise applications. Its portfolio spans wired and wireless connectivity, storage, cloud infrastructure, and IoT technologies, with teams working closely with partners to tailor products to changing technical and business requirements. The company’s hiring context is rooted in advanced semiconductor manufacturing, infrastructure engineering, consulting, and enterprise technology.

Marvell Digital IC Design Intern (BS) - Santa Clara, CA

Join Marvell as a Digital IC Design Intern to develop and verify RTL blocks for cloud, AI, storage, and networking semiconductor products. Gain hands-on experience with ASIC design, timing, synthesis, and power analysis.

Description

  • Contribute to digital design and implementation for active chip projects
  • Design and verify detailed, high-performance RTL blocks
  • Translate digital design specifications into solutions for high-speed connectivity devices and next-generation chips
  • Perform synthesis, static timing analysis, timing signoff, and power analysis
  • Troubleshoot design issues and validate functional correctness
  • Evaluate and implement new design techniques and flows
  • Investigate emerging methodologies that improve design quality, efficiency, and productivity
  • Work with chip architecture, design verification, and physical design teams
  • Address complex engineering challenges while contributing to production semiconductor products

Requirements

  • Currently pursuing a bachelor’s degree in electrical engineering, computer engineering, or a related discipline
  • Graduation expected between fall 2027 and summer 2028
  • Coursework in areas such as circuit design, circuit theory, digital logic, static timing analysis, computer architecture, Verilog, VLSI, DSP, SoC or ASIC design, or electronics
  • Proficiency with programming and scripting languages including Python, Perl, or Tcl
  • Experience with Synopsys PrimeTime, Cadence Virtuoso and Spectre X, and Mentor tools
  • Practical RTL design experience and an understanding of how RTL integrates into the broader ASIC design flow
  • Strong analytical, problem-solving, and communication abilities
  • Eligibility to access export-controlled information under applicable U.S. law; some applicants may require export license review

Benefits

  • Medical, dental, and vision insurance coverage
  • Employee perks and discount programs
  • Comprehensive mental health resources
  • Paid holidays
  • Potential additional compensation for PhD interns

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