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Senior ASIC Digital Design Lead, Silicon Photonics
Lead digital design for Cisco silicon photonics and high-speed optical networking solutions, spanning ASIC and CPU subsystem logic. Work across architecture, verification, tapeout, and post-silicon validation.
विवरण
- Lead digital logic development for silicon photonics and high-speed optical interconnects.
- Guide ASIC development from architecture and RTL design through tapeout and post-silicon production support.
- Coordinate digital logic integration with analog and mixed-signal blocks in Co-Packaged Optics and silicon photonics modules.
- Set digital architecture, interface requirements, implementation plans, and design methods.
- Lead block and top-level design, along with block-level verification.
- Support full-chip integration of high-speed IP, including ODSP, D2D IP, SerDes XSR, SerDes PAM4 integrated drivers and TIA, and control functions.
- Work with verification teams to reach functional closure and meet sign-off coverage metrics.
- Prepare designs for physical implementation and support post-silicon bring-up and production release.
- Contribute from pre-silicon RTL through GDS2 sign-off, then support FPGA prototyping, lab validation, and ATE bring-up.
- Design complex digital blocks and CPU subsystems, resolving design and technical issues.
- Translate top-level specifications into block-level requirements for high-speed datapaths and low-speed control planes.
- Support synthesis, timing closure, DFT, low-power design, automation scripts, and QOR metric processing.
- Take part in FPGA prototyping and validation.
आवश्यकताएँ
- Bachelor’s or master’s degree in electrical engineering, electronics engineering, or a related discipline; a master’s degree is preferred.
- 8–12 years of industry experience in digital design, including FSMs, CPU subsystems, complex SoCs, and FPGA validation.
- Familiarity with SPI, I2C, APB, AXI, or comparable interfaces.
- Familiarity with high-speed SerDes, Ethernet, D2D PHY IP, and related protocols.
- Strong understanding of ASIC and SoC design flows.
- Experience developing RTL with SystemVerilog and using simulation, lint, CDC/RDC, synthesis, formal or equivalence checking, DFT, and implementation handoff.
- Solid understanding of front-end design and development.
- Exposure to backend tools and activities, including CDC, synthesis, LEC, and DFT.
- Strong collaboration, communication, and organizational abilities.
- Strong analytical, debugging, and problem-solving skills.
लाभ
- Opportunities to develop your career at Cisco.
- Collaboration with experts around the world.
- Work on optical transceivers, silicon photonics, and networking solutions.
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