Codasip
Codasip
Codasip RISC-V texnologiyasi, xavfsiz kremniy va funksional xavfsizlikka ixtisoslashgan yarimo‘tkazgich intellektual mulki hamda protsessor dizayni kompaniyasidir. Uning portfeliga CHERI qo‘llab-quvvatloviga ega 64 bitli RISC-V amaliy yadrolari, o‘rnatilgan tizimlar va avtomobillar uchun protsessorlar, shuningdek Codasip Studio va CodAL tili kabi loyihalash vositalari kiradi. Kompaniya avtomobilsozlik, mudofaa, avionika, sanoat tizimlari va muhim infratuzilma kabi yuqori talabga ega bozorlar uchun standart protsessor intellektual mulki hamda moslashtirilgan platformalarni ishlab chiqadi. Uskuna va kiberxavfsizlik yo‘nalishlarida ishlaydigan Codasip jamoalari tartibga solinadigan ilovalarning xavfsizlik va ishonchlilik ehtiyojlarini qondirishga mo‘ljallangan protsessor texnologiyalarini yaratadi.

Verification Engineer – RISC-V CPUs (Hybrid, Czechia)

Join Codasip to verify RISC-V processors and extensions within a secure semiconductor architecture company. Build automated verification flows for advanced CPU designs.

Tavsif

  • Validate RISC-V processors and processor extensions
  • Create verification solutions spanning testbenches, testbench components, stimulus generation, and formal environments
  • Work with engineers to complete verification activities for components and subsystems
  • Establish verification strategies for blocks and subsystems and choose suitable tools
  • Assess technical specifications and provide feedback focused on verification
  • Execute simulations, investigate defects, and determine root causes for complex issues
  • Plan, estimate, prioritize, and monitor assigned work
  • Measure and report verification performance metrics
  • Develop automated verification workflows
  • Verify advanced CPUs, including complex out-of-order processor designs
  • Own designated areas of the design and apply multiple verification approaches

Talablar

  • Be currently based in the Czech Republic and have the right to work there
  • Have commercial experience applying functional processor verification methods to CPUs or other ASICs, including simulation, test generation, coverage analysis, and gate-level simulation
  • Understand verification of CPU architectures or other intellectual property
  • Write clear, concise code in SystemVerilog, Python, C++, Rust, or a comparable language
  • Have previously owned verification for a design block
  • Use Linux to automate routine tasks
  • Know version-control tools such as Git and SVN
  • Understand the RISC-V architecture
  • Have a strong understanding of computer systems and architecture
  • Demonstrate analytical thinking and collaborative team skills
  • Work effectively across teams to debug problems and identify root causes

Imtiyozlar

  • The posting does not specify benefits, perks, or additional compensation.

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