Analog Devices
Analog Devices
Analog Devices develops and manufactures analog, mixed-signal, and digital signal processing integrated circuits for demanding applications across automotive, industrial automation, healthcare, communications, and consumer electronics. Its portfolio includes GMSL technology, which supports high-speed connectivity in vehicles and other connected systems. The company’s work spans sensing, signal processing, and connectivity, helping enable smart driving platforms and high-performance electronic products.

Associate Design Verification Engineer Dallas Onsite

Join Analog Devices as an Associate Design Verification Engineer validating digital, analog, and mixed-signal integrated circuits. Build SystemVerilog test benches, analyze coverage, and automate simulation workflows.

Description

  • Help verify digital, analog, and mixed-signal integrated circuits before tape-out
  • Build and run SystemVerilog test benches using established verification methods
  • Develop and maintain functional and coverage-driven verification environments
  • Create directed and constrained-random tests to validate design functionality and performance
  • Analyze code and functional coverage results
  • Investigate simulation failures, interpret verification data, and flag potential design issues
  • Work with design engineers to clarify requirements and confirm implementation accuracy
  • Assist with verification plans, technical documentation, and design reviews
  • Apply scripting and automation to improve verification efficiency and productivity
  • Support mixed-signal simulation and behavioral modeling activities when needed
  • Partner with cross-functional engineering teams to deliver reliable semiconductor products
  • Travel approximately 10% of the time

Requirements

  • Knowledge of SystemVerilog and digital verification fundamentals, including test bench creation and simulation-based validation
  • Understanding of RTL design principles and the ability to assess digital hardware implementations
  • Familiarity with coverage-driven verification and structured verification practices
  • Experience or academic work with Python, Perl, or Tcl for automation and productivity improvements
  • Understanding of communication protocols such as I2C, SPI, UART, or comparable interfaces
  • Ability to interpret simulation results, troubleshoot failures, and resolve technical problems
  • Clear written and verbal communication skills with the ability to collaborate effectively
  • Bachelor’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, Computer Science, or a related discipline preferred
  • 0–2 years of experience in digital design verification or a related engineering field
  • Relevant projects, internships, or coursework in digital design, verification, or semiconductor engineering welcomed for new graduates
  • Exposure to UVM, constrained-random verification, or SystemVerilog Assertions is advantageous
  • Familiarity with EDA simulation and debugging tools preferred
  • Exposure to mixed-signal simulation, analog behavioral modeling, or object-oriented programming is beneficial
  • Eligibility for U.S. export-control requirements may be needed to access certain technical data

Benefits

  • Employee programs and support offerings
  • Opportunities for ongoing professional learning
  • Workplace practices focused on sustainability and the future

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